1. Field of the Invention
The present invention relates to a circuit module which is operated at a high-speed operation and which is mounted in a high density, and an electrical component used for the circuit module.
2. Description of the Related Art
A high speed operation and a high density mounting have been required of a circuit module, such as a memory module. As an economical high-density mounting technology, recent interest has been mainly directed to stacking solid-state circuit elements in order to mount the circuit module in a high density. In a silicon semiconductor which has presently mainly been used, a proposal has been offered about a technology which perforates a silicon substrate itself to connect upper and lower elements on the silicon substrate to one another. However, this technology still remains inferior to stacking at a package level from the viewpoint of cost.
In Japanese Unexamined Patent Application Publication Nos. 2006-49838, 2001-53243, 2002-368185, and the like, stacking at a package level is performed to form a stacked package and to thereby realize high-density mounting.
Specifically, Japanese Unexamined Patent Application Publication No. 2006-49838 proposes to use balls in order to connect stacked chips to a tape or a substrate member. In addition, Japanese Unexamined Patent Application Publication Nos. 2001-53243 and 2002-368185 propose to use leads and to use a metal compression-bonding method, respectively.
Moreover, Japanese Unexamined Patent Application Publication No. 2002-110856 discloses a manufacturing method for a semiconductor device wherein an interposer individually separated for each element is prepared and is mounted only on a defect-free semiconductor chip on a semiconductor wafer, and electrode pads of the defect-free semiconductor chip and inner bumps of the interposer are bonded together by thermo-compression bonding. Thereafter, the semiconductor chip is individually separated from the semiconductor wafer. In this case, a surface size of the interposer can be equal to or smaller than that of the semiconductor chip and therefore a semiconductor device can be small in size.
Furthermore, Japanese Unexamined Patent Application Publication No. 2004-327474 proposes a technique of shortening a wiring length for an upper-stage device by providing a through hole passing through a device chip itself.
Japanese Unexamined Patent Application Publication Nos. 2006-49838, 2001-53243, and 2002-368185 can realize the high-density mounting by stacking semiconductor chips at a package level, but do not point out any problems which might be caused to occur on stacking the semiconductor chips at a package level.
Further, Japanese Unexamined Patent Application Publication No. 2002-110856 discloses that the surface size of the interposer which supports the semiconductor chip can be equal to or smaller than that of the semiconductor chip and therefore the semiconductor device can be small in size. In this case, the interposer can be smaller than the semiconductor chip by a size such that each semiconductor chip supported by the interposer can be cut out. For that reason, the semiconductor chip supported by the interposer does not keep large space enough to be opposed to another semiconductor chip.
The technique of Japanese Unexamined Patent Application Publication No. 2004-327474 needs to mechanically process chips. Therefore, the technique does not propose any method of solving any problem related to a package alone.